Use of gate electrode workfunction to improve DRAM refresh

ABSTRACT

This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

FIELD OF THE INVENTION

[0001] This invention relates to the field of semiconductor memorycircuits, and particularly to a method of improving DRAM refresh byusing midgap or near midgap materials, such as silicon germanium, intransistor gate electrodes for tuning workfunction and thresholdvoltages in DRAM access transistors, so as to minimize current leakage.

BACKGROUND OF THE INVENTION

[0002] Doping of semiconductor substrates to form semiconductor devicesis a well known practice in the art. To form memory devices, not onlyare the underlying substrate and source and drain regions implanted withdopant, but most often the conductive elements of the transistor gatesare doped as well. In modern DRAM processing, typical and almostuniversal doping patterns for transistors in the prior art includeutilizing a N+ doped polysilicon (poly) for the access transistor gates,N+ doped poly for periphery NMOS transistor gates, and N+ doped poly forperiphery PMOS transistor gates. A new trend in the industry is toutilize a P+ doped poly for the periphery PMOS transistor gates.

[0003] In semiconductor device manufacture, a known problem is that asgate lengths of transistors are scaled to shorter and shorter lengthsand gate dielectrics are reduced, the doping levels of the underlyingchannel region of the substrate must be increased to maintain sufficientaccess device threshold voltages (V_(t)). Current leakage is a problemwith modern memory devices associated with such doping. There are twocomponents to leakage: (1) transistor leakage, which may be reduced byincreasing the substrate doping in the channel region, and thusincreasing the V_(t); and (2) diode leakage of the source/drainjunction. A major problem is that efforts to alleviate one leakageproblem worsens the other. For example, while increasing the channelregion substrate doping raises V_(t) and reduces the transistor leakageproblem, it worsens the diode leakage. Hence, when access devices aremanufactured by current processes, they must be designed to balancetheses two leakage components, which is becoming increasingly moredifficult to do. Another problem is that as the array (channel region)doping levels increase in a DRAM array to set sufficient thresholdvoltage for the access transistor, DRAM refresh characteristics suffer.

[0004] To scale the DRAM die size smaller, the transistor gate lengthsin both the array and periphery must be reduced. To support the shortergate lengths and to minimize the power dissipation of increasing DRAMdensity, the operation voltage is reduced. The lower operating voltageand the reduction in gate length dictate that the gate dielectric isreduced to maintain sufficient switching performance. For NMOStransistors with N+ poly gate electrodes, as the gate oxide is reducedit is required to increase the channel doping to maintain a sufficientlyhigh access threshold voltage.

[0005] In DRAM technology, a stored “one” will gradually become a “zero”as electrons refill the empty well. This phenomenon is the leakagedescribed above. The nature of the one transistor DRAM cell is that“ones” gradually become “zeros” and “zeros” remain so. This phenomenonrequires that the memory cell be refreshed periodically to maintain thecorrect data storage at each bit location. The total leakage current ofthe cell must be low enough that the cell does not discharge and loseits memory state. If a transistor could be designed to have less leakagecurrent, the refresh characteristics of the DRAM would be improved.

[0006] It would be useful in DRAM device manufacturing to utilize amethod of tailoring transistor threshold voltages specifically for thevarious transistors that required less channel dopant. It would bepreferable if this tailoring of V_(t) could be accomplished whilereducing the memory array substrate channel doping levels so as tominimize current leakage and improve refresh characteristics.Additionally, use of novel materials, that could be readily incorporatedinto standard DRAM processing, for transistor gate electrodes toaccomplish the above would be advantageous.

SUMMARY OF THE INVENTION

[0007] This invention relates to a method of forming a DRAM structureand the resulting structure. This method uses selected amounts ofsilicon midgap or near midgap materials for transistor gate electrodes,and thus tailors the workfunction of the gate electrodes. In sotailoring the workfunction of the gate electrodes, a DRAM memory devicecan be formed with a threshold voltage set to a sufficiently high level,while allowing an accompanying reduction in the array substrate channeldoping requirements for a given target V_(t) of the DRAM transistor. Bythis method, novel DRAM access and periphery logic transistors may beformed, having a threshold voltage tailored to a sufficient level, withaccordingly reduced channel region substrate doping, resulting inminimized transistor and diode current leakage, and ultimatelyeffectuating improvements in the refresh characteristics of the DRAMdevice.

[0008] These and other features and advantages of the invention will bemore clearly understood from the following detailed description of theinvention which is provided in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is an illustration of an access transistor formed inaccordance with the invention;

[0010]FIG. 2 is an illustration of periphery transistors formed inaccordance with the invention;

[0011]FIG. 3 is a depiction of a processor based system incorporatingthe transistors shown in FIG. I and FIG. II.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DRAM memory circuits are currently the most popular type ofmemory circuits used as the main memory of processor-based systems.Therefore, the invention will be discussed in connection with DRAMmemory circuits. However, the invention herein disclosed has broaderapplicability and is not limited to DRAM memory circuits. It may be usedin any other type of MOS transistor circuit, in which it is desired toreduce the amount of dopant required to run sufficiently high thresholdvoltages, and so as to minimize current leakage. Particularly applicableto DRAM technology, however, is the characteristic of the invention thatrefresh characteristics of a DRAM memory device can be improved.

[0013] Also, the terms “wafer” and “substrate” are used interchangeablyand are to be understood as including silicon, silicon-on-insulator(SOI), and silicon-on-sapphire (SOS) technology, and other semiconductorstructures. Furthermore, references to a “wafer” or “substrate” in thefollowing description, do not exclude previous processing steps utilizedto form regions or junctions in or on the base semiconductor structureor foundation.

[0014] No particular order is required for the method steps describedbelow, with the exception of those logically requiring the results ofprior steps. Accordingly, while many of the steps discussed below arediscussed as being performed in an exemplary order, this order may bealtered.

[0015] The present invention provides a method of forming a DRAM havinga memory array access transistor and periphery logic transistors on anintegrated circuit. These transistors follow standard MOS transistorprocessing steps, but with materials alternatives for the transistorgate electrodes. During processing, the transistor gate electrodes canbe formed incorporating silicon (Si) midgap or near midgap (hereinaftermidgap) materials. Such materials refer to those having a workfunctionfalling between that of P+Si and N+Si, or more specifically, between theconduction band and valence band of Si. These materials include thosesuch as Si/Ge, TiN/W, Al/TiN, and Ti/TiN, all of which are commonly usedin semiconductor devices. By altering the mole fraction of the midgapmaterial used in a given transistor gate electrode, the workfunction ofthe electrode is tailored, thus the threshold voltage can be tailoredand increased without necessitating any increase in underlying channeldoping levels. Consequently, standard V_(t) may be achieved using areduced channel doping. This helps in reducing current leakage andimproves access transistor refresh characteristics.

[0016] Referring now to the drawings, where like elements are designatedby like reference numerals, in accordance with the process of theinvention, an access transistor of a DRAM can be formed as shown in FIG.I. FIG. I shows a conventional DRAM memory device, but the process ofthe invention modifies this structure by using midgap materials for thegate electrode to tailor its workfunction. An access transistor gatestack 10, source and drain regions 18, and any subsequent devices, areformed substantially as known in the art, with novel variations asdescribed below. Because the materials for transistor gate electrodesutilized in accordance with this invention are readily integrated intostandard MOS processing, all processing steps according to thisinvention clan be performed as is known in the art.

[0017] The access transistor is formed over a substrate 22, preferablysilicon or a compound including silicon (Si) and germanium (Ge), with asurface upon which the gate structure 10 rests. The access transistorgate stack 10 includes a bottom gate oxide 12, a gate electrode 14/16comprising a midgap material, a gate top insulator cap 17, and sideoxide, or nitride, spacers 20. The entire gate electrode, parts 14 and16, may comprise the midgap material, or the bottom portion 14 maycomprise the midgap material while the top portion 16 comprisespolysilicon or some other conductive material. The processing stepsutilized in forming the gate electrode 14/16 to achieve the advantagesof the invention are discussed below. On either side of the gate stack10 are source and drain regions 18 to form a transistor. The gate stack10 is positioned between the source and drain regions 18, forming achannel region 19 between the source and drain regions 18. A memory cellis completed with the capacitor 24, and the bit line and plug 26.

[0018] Also in accordance with the invention, periphery logictransistors can be formed as shown in FIG. II. Again, FIG. II showsconventional transistor structures, but the process of the inventionmodifies these structures by using midgap materials for the transistorgate electrodes as will be further discussed below. These gatestructures can include a periphery NMOS transistor gate stack 30 and aperiphery PMOS transistor gate stack 40. These NMOS and PMOS transistorsare formed over the same substrate 22, and can be on the same integratedcircuit, as the access transistor gate stack 10 shown in FIG. I. Theperiphery NMOS and PMOS transistor gate stacks 30, 40 include a gateoxide 12, a NMOS gate electrode 32/34 comprising a midgap material or aPMOS gate electrode 42/44 comprising a midgap material, a gate topinsulator cap 17, and side oxide, or nitride, spacers 20. As with theaccess transistor described above, the entire gate electrode of eachtransistor, portions 32 and 34, and portions 42 and 44, can comprise themidgap material. Alternatively, the bottom portions of the gateelectrodes 32 and 42 can comprise the midgap material, while the topportions 34 and 44 comprise polysilicon or another conductive material.On either side of the NMOS gate stack 30 are N-type source and drainregions 36 to complete the periphery NMOS transistor. On either side ofthe periphery PMOS gate stack 40 are P-type source and drain regions 46to complete the periphery PMOS transistor. Each transistor can beisolated within the substrate 22 by a FOX (field oxide) region 50. Theperiphery logic circuits can be completed by interconnect lines 52.

[0019] By using midgap materials, such as silicon germanium (Si/Ge), forthe DRAM array and periphery logic transistor gate electrodes andmanipulating the mole fraction of this material in accordance with theinvention, the workfunction of the gate electrodes can be tailored andthe concentrations of dopants necessary to form the memory and logicdevice channels to achieve a desired threshold voltage can be less thanis required in the prior art, thereby decreasing current leakage andimproving refresh characteristics of the DRAM memory array.Additionally, in accordance with this invention, it is also possible toutilize P+ polysilicon alone for the memory array transistor gateelectrode to similarly reduce the memory array channel dopantrequirements; essentially using a “zero” mole fraction of the midgapmaterial.

[0020] Before an MOS (metal oxide semiconductor) transistor structure,such as those described herein, is formed, the electrons in thesemiconductor and the gate metal (or polysilicon) are at differentpotentials with respect to a vacuum (common reference). When thematerials are brought together, equilibrium must be achieved in thesystem.

[0021] This equilibrium is naturally achieved by the flowing ofelectrons to regions of lower potential until an internal electric fieldis built up, thus forming a depletion region, which balances theoriginal electric-potential difference. The difference between theelectron potentials in the metal or polysilicon, used for the transistorgate electrodes, as compared to the silicon substrate must be consideredwhen setting the device V_(t) and performing the silicon substratedoping. Hence, the electron potential in the metal or poly, with respectto the vacuum, plays a factor in determining the final V_(t) of thedevice, as well as determining related characteristics. Furthermore, thepotential (workfunction) in the metal/poly is a characteristic propertyof the material itself. The use of different materials, such as thosedescribed herein, can increase a transistor's V_(t), thereby allowing anaccompanying reduction in the substrate doping for a given target V_(t).This results in improved access transistor refresh.

[0022] Use of non-traditional materials, such as polycrystalline Si/Ge,for gate electrode materials for access transistors, and periphery NMOSand PMOS transistors, provides a minimized poly-depletion effect andboron penetration, and the gate workfunction may be tailored bycontrolling the Ge (or other midgap material) mole fraction in relationto the Si/Ge. By changing the Ge (or other midgap material) molefraction in the poly-Si/Ge films used here, a threshold voltage (V_(t))adjustment may be achieved with reduced channel doping levels for agiven gate oxide thicknesses. By this process, improved current driveand transconductance may be achieved in the silicon germanium gatedevices compared to traditional polysilicon gate devices. Theseimprovements in materials technology can be readily implemented intostandard DRAM processing. In such a DRAM device, refresh is improved.

[0023] DRAM refresh is improved by this tailoring of the workfunction ofthe access transistor, which allows for less boron dopant enhancementimplant. By using a mole fraction of 0.0 to 0.7 Ge for P+ type gateelectrodes for access transistors, such work function tailoring isachieved, thereby enabling a sufficient threshold voltage for thetransistor while using less dopant, as compared to the N+ polysilicongate electrodes currently used in the art. The less germanium used in asilicon germanium gate electrode, the less enhancement implant neededfor a given V_(t), but the worse the short channel effects (worse punchthrough) for the access transistor will be. Conversely, using moregermanium for a higher mole fraction requires a higher dopantconcentration, but provides superior short channel effects. Thus, for agiven technology (gate length, operating voltage, design of the memoryarray S/D structure including LDD design, etc.), there will be anoptimum value of Ge mole fraction. For standard DRAM technology, nominal0.3 Ge and 0.7 Si provides the desired improved refresh characteristicsand appropriate V_(t) with reduced leakage.

[0024] By utilizing the materials and process of the invention, the stepof masking and re-implanting the wafer with boron for an enhancementimplant to selectively increase the memory array transistor gate V_(t),which would normally be performed in the prior art, can be omitted,thereby reducing the overall number of processing steps required. In theprior art, this step would be performed to help set the V_(t), of thememory array access transistors. This boron implant would increase thedoping of the regions under the transistor gates, which form channels19. Because of the novel use of midgap materials for gate electrodes,the invention makes such additional implanting potentially unnecessaryand provides for fewer steps, while resulting in devices with improvedleakage and refresh characteristics, while maintaining other standardperformance levels.

[0025] Transistor gates are formed as shown in FIG. I and II. It ispossible to form all transistors, including the periphery NMOS and PMOStransistors, by this process, but it will here be explained using DRAMaccess transistor processing as an example.

[0026] The materials for the gate electrode 14/16 are deposited overgate oxides 12. Use of midgap materials for at least a portion (14) ofthe gate electrode 14/16 is necessary to adjust the workfunction of thegates in accordance with the invention. A good example of a midgapmaterial that may be utilized in accordance with this invention issilicon germanium (Si/Ge). Silicon germanium may be used alone, orincorporated with a polysilicon upper-layer 16, as the gate electrodematerial for DRAM transistors. Silicon germanium can be readilyintegrated as a gate material into existing DRAM technology to achievesignificant increases in transistor performance. This will be theexemplary embodiment used for exemplary purposes.

[0027] The Ge mole fraction of the poly-Si/Ge gate electrode 14/16 isoptimized from about 0.2 to 0.7 Ge mole fraction. Ge is a neutralspecies suitable for both P and N-type transistors. By tuning the Gemole fraction, the desired threshold voltage value can be set, andchannel dopings for access transistors, and NMOS and PMOS peripherytransistors can be optimized to improve refresh considerations asdiscussed. The target array transistor V_(t) should be tailored by thismethod to be about 200-800 mV higher than the counterpart periphery NMOStransistor.

[0028] The completed DRAM access transistor gate stack 10 will have thestructure illustrated in FIG. I, wherein the gate electrode 14/16 can beentirely composed of Si/Ge, or alternatively, the bottom portion of theelectrode 14 can be Si/Ge while the top portion of the gate electrode 16is a doped polysilicon or other conductive layer. The fabrication ofthis gate structure can be accomplished by deposition of the Si/Ge byrapid thermal chemical vapor deposition (RTCVD) or by LPCVD. A gasmixture comprising Si₂H₆ and GeH₄ may be used.

[0029] It is also possible to implant the desired amount of Ge into apre-deposited layer of polysilicon. This is accomplished by a very highdose Ge implantation (many atomic % of GE, similar to SIMOX doselevels).

[0030] If it is desired to utilize a polysilicon cap layer 16 over theSi/Ge gate electrode layer 14, this may be accomplished by conventionalprocessing as known in the art. Such a cap 16 may be desired for justsuch a purpose: to remain as close as possible to conventionalpolysilicon gate processing. To form this polysilicon layer, lowpressure chemical vapor deposition (LPCVD) may be used. Siliane gas(SiH₄) is used to form this layer of the transistor gate. It is alsopossible to replace or add to this cap layer 16 with a more conductivematerial such as a silicide.

[0031] After the formation of the gate oxide 12, the midgap transistorgate electrode 14, and the cap layer 16 (if desired), the top layer ofthe access transistor gate stack 10, the dielectric cap 17, is formed.After the forming of this dielectric cap layer, the gate stacks can bepatterned and etched as known in the art. Next, the source and drainregions 18 can be formed by ion implantation and gate oxide spacers 20can be formed as is known in the art to complete the access transistoras shown in FIG. I. After the fabrication of the gate and source anddrain regions, subsequent processing can continue as known in the art,including the forming of capacitors 24, bit lines and plugs 26, and cellmetallization (not shown).

[0032] As an alternative processing method, the transistors can befabricated utilizing the method described in U.S. Pat. No. 5,824,576,incorporated herein by reference. This process allows for a reduction inthe number of related masking steps. The midgap or near midgap materialsdiscussed herein can be incorporated into this alternative processingmethod so that the transistor gate electrode workfunctions and thresholdvoltages are tailored in a similar fashion to that discussed above toallow a reduction in doping requirements and improved device currentleakage characteristics.

[0033] FIG. III illustrates a processor system (e.g., a computersystem), with which a memory having a memory cell area and a peripherylogic area as described above may be used. The processor systemcomprises a central processing unit (CPU) 102, a memory circuit 104, andan input/output device (I/O) 100. The memory circuit 104 contains aDRAM, or other memory device, including semiconductor devicesconstructed in accordance with the present invention. Also, the CPU 102may itself be an integrated processor, which utilizes semiconductordevices constructed in accordance with the present invention, and boththe CPU 102 and the memory circuit 104 may be integrated on a singlechip, so as to fully utilize the advantages of the invention.

Alternative Embodiments

[0034] In each embodiment set forth below, the specific structure may beachieved by utilizing the processing methodology described above inrelation to FIG. I-III. These alternative embodiments are intended tofurther describe the invention. They are not intended to limit the scopeof the invention to any single embodiment or combination.

[0035] For each embodiment described below, the range of mole fractionfor the midgap material can range from 0.0 to 0.7 Ge for the accesstransistors. The preferred ratio is 0.3 Ge to 0.7 Si for the gateelectrode materials. The access transistors are NMOS type transistors.

Embodiment 1

[0036] In the first embodiment, the semiconductor device structure hasaccess transistors comprising P+ Si/Ge gate electrodes 14, peripheryNMOS transistors comprising P+ Si/Ge gate electrodes 32 and peripheryPMOS transistors comprising P+ Si/Ge gate electrodes 42.

Embodiment 2

[0037] In the second embodiment, the semiconductor device structure hasaccess transistors comprising P+ Si/Ge gate electrode 14, a majority ofperiphery NMOS transistors comprise N+ Si/Ge gate electrodes 32, and aminority of periphery NMOS transistors comprise P+ Si/Ge gate electrodes32, and a majority of the periphery PMOS transistors comprise P+ Si/Gegate electrode 42, and a minority comprise N+ Si/Ge gate electrodes 42.

Embodiment 3

[0038] For the third embodiment, the semiconductor device structure hasaccess transistors comprising either N+ or P+ Si/Ge gate electrodes 14,a majority of periphery NMOS transistors comprise a N+ poly gateelectrodes 32, and may have a minority comprise either P+ poly or Si/Gegate electrodes 32, and periphery PMOS transistors comprise either P+poly or N+ poly gate electrodes 42.

Embodiment 4

[0039] For the fourth embodiment, the semiconductor device structure hasaccess transistors comprising P+ poly gate electrodes 14, periphery NMOStransistors comprising N+ poly gate electrodes 32, and periphery PMOStransistors comprising P+ poly gate electrodes 42. This embodimentessentially has a 0.0 mole fraction of Ge and may result in theconversion of the access transistor from a surface channel device to apotentially buried channel device, resulting in added challenges tominimize access transistor leakage. However, this embodiment requiresthe least amount of boron implant, and may even require an N-type arrayimplant adjust. With the use of very steep implants, such as antimony orarsenic, for the V_(t) adjust and very shallow LDDs along with a borondeep punchthrough implant, it is possible to make it an accesstransistor with acceptable characteristics of acceptable the drain tosource leakage. Also the use of a negative voltage wordline in the offstate may enable this process, allowing better “off” characteristics andless leakage.

[0040] The above description and accompanying drawings are onlyillustrative of exemplary embodiments, which can achieve the featuresand advantages of the present invention. It is not intended that theinvention be limited to the embodiments shown and described in detailherein. While the invention has been illustrated primarily with Si/Ge,other materials, such as TiN/W, Al/TiN, and Ti/TiN, can also be used.The invention can be modified to incorporate any number of variations,alterations, substitutions or equivalent arrangements not heretoforedescribed, but which are commensurate with the spirit and scope of theinvention. The invention is only limited by the scope of the followingclaims.

What is claimed as new and desired to be protected by Letters Patent of the U.S. is:
 1. A DRAM device comprising: at least one NMOS access transistor having a gate electrode comprising a midgap material containing at least two material components, the threshold voltage of said access transistor being set at least in part by the mole fraction of said midgap material components of said gate electrode of said access transistor; and at least one first periphery logic transistor having a gate electrode comprising a midgap material containing at least two material components, the threshold voltage of said at least one first periphery logic transistor being set at least in part by the mole fraction of said midgap material components of said gate electrode of said periphery logic transistor.
 2. The DRAM device of claim 1, further comprising at least one second periphery logic transistor having a gate electrode comprising a midgap material containing at least two material components, wherein the threshold voltage of said at least one second periphery logic transistor is set at least in part by the mole fraction of said midgap material components of said gate electrode of said second periphery logic transistor, wherein said at least one first periphery logic transistor is a NMOS transistor and said at least one second periphery logic transistor is a PMOS transistor.
 3. The DRAM device of claim 2, wherein said midgap material comprises silicon germanium.
 4. The DRAM device of claim 3, wherein said mole fraction of said silicon germanium of said at least one access transistor is within the range of 0.0 to 0.7 germanium.
 5. The DRAM device of claim 4, wherein said mole fraction of said silicon germanium of said at least one access transistor is at least 0.2 germanium.
 6. The DRAM device of claim 5, wherein said silicon germanium of said at least one access transistor comprises about 30% germanium and 70% silicon.
 7. The DRAM device of claim 2, wherein said mole fraction of said midgap material of the gate electrode of each said transistor is such that said threshold voltage of said at least one access transistor is about 200-800 mV higher than threshold voltage of said at least one first periphery logic transistor.
 8. The DRAM device of claim 4, wherein said gate electrode of said at least one access transistor comprises P+ silicon germanium; said gate electrode of said at least one first periphery logic transistor comprises P+ silicon germanium; and said gate electrode of said at least one second periphery logic transistor comprises P+ silicon germanium.
 9. The DRAM device of claim 4, further comprising a plurality of said first and second periphery logic transistors, wherein said gate electrode of said at least one access transistor comprises P+ silicon germanium; a majority of said gate electrodes of said first periphery logic transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said first periphery logic transistors comprise P+ silicon germanium; and a majority of said gate electrodes of said second periphery logic transistors comprise P+ silicon germanium, and a minority of said gate electrodes of said second periphery logic transistors comprise N+ silicon germanium.
 10. The DRAM device of claim 4, further comprising a plurality of said first and second periphery logic transistors, wherein said gate electrode of said at least one access transistor comprises either N+ or P+ silicon germanium; a majority of said gate electrodes of said first periphery logic transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said first periphery logic transistors comprise P+ silicon germanium; and said gate electrodes of said second periphery logic transistors comprise either P+ or N+ silicon germanium.
 11. The DRAM device of claim 4, further comprising a plurality of said first and second periphery logic transistors, wherein said gate electrode of said at least one access transistor comprises P+ silicon germanium; said gate electrodes of said first periphery logic transistors comprise N+ silicon germanium; and a majority of said gate electrodes of said second periphery logic transistors comprise P+ silicon germanium.
 12. The DRAM device of claim 4, wherein said gate electrode of at least one of said at least one access transistor, said at least one first periphery logic transistor, and said at least one second periphery logic transistor, comprises a layer of polysilicon over a layer of said midgap material.
 13. A memory device, comprising: a NMOS memory array access transistor having a gate electrode comprising a midgap material containing at least two material components, the threshold voltage of said gate electrode of said memory array access transistor being set at least in part by the mole fraction of said midgap material components of said gate electrode of said memory array access transistor and a concentration of channel dopant reduced in accordance with said mole fraction of said midgap material components of said gate electrode of said memory array access transistor; a first periphery logic transistor having a gate electrode comprising a midgap material containing at least two material components, the threshold voltage of said gate electrode of said first periphery logic transistor being set at least in part by the mole fraction of said midgap material components of said gate electrode of said first periphery logic transistor and a concentration of channel dopant reduced in accordance with said mole fraction of said midgap material components of said gate electrode of said first periphery logic transistor; and a second periphery logic transistor having a gate electrode comprising a midgap material containing at least two material components, the threshold voltage of said gate electrode of said second periphery logic transistor being set at least in part by the mole fraction of said midgap material components of said gate electrode of said second periphery logic transistor and a concentration of channel dopant reduced in accordance with said mole fraction of said midgap material components of said gate electrode of said second periphery logic transistor.
 14. The memory device of claim 13, wherein said memory array access transistor is part of a DRAM array, said first periphery logic transistor is a NMOS transistor and said second periphery logic transistor is a PMOS transistor, each said transistor being on the same integrated circuit.
 15. The memory device of claim 14, wherein said midgap material of said memory array access transistor is silicon germanium.
 16. The memory device of claim 13, wherein said mole fraction of said midgap material components of said memory array access transistor and said mole fraction of said midgap material components of said first periphery logic transistor are such that said threshold voltage of said memory array access transistor is about 200-800 mV higher than that of said first periphery logic transistor.
 17. The memory device of claim 14, wherein said mole fraction of said silicon germanium of said memory array access transistor is within the range of 0.0 to 0.7 germanium.
 18. The memory device of claim 17, wherein said mole fraction of said silicon germanium of said memory array access transistor is at least 0.2 germanium.
 19. The memory device of claim 18, wherein said silicon germanium of said memory array access transistor comprises about 30% germanium and 70% silicon.
 20. The memory device of claim 17, wherein said gate electrode of said memory array access transistor comprises P+ silicon germanium; said gate electrode of said first periphery logic transistor comprises P+ silicon germanium; and said gate electrode of said second periphery logic transistor comprises P+ silicon germanium.
 21. The memory device of claim 17, further comprising a plurality of said first and second periphery logic transistors, wherein said gate electrode of said memory array access transistor comprises P+ silicon germanium; a majority of said gate electrodes of said first periphery logic transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said first periphery logic transistors comprise P+ silicon germanium; and a majority of said gate electrodes of said second periphery logic transistors comprise P+ silicon germanium, and a minority of said gate electrodes of said second periphery logic transistors comprise N+ silicon germanium.
 22. The memory device of claim 17, further comprising a plurality of said first and second periphery logic transistors, wherein said gate electrode of said memory array access transistor comprises either N+ or P+ silicon germanium; a majority of said gate electrodes of said first periphery logic transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said first periphery logic transistors comprise P+ silicon germanium; and said gate electrodes of said second periphery logic transistors comprise either P+ or N+ silicon germanium.
 23. The memory device of claim 17, further comprising a plurality of said first and second periphery logic transistors, wherein said gate electrodes of said memory array access transistor comprises P+ silicon germanium; said gate electrodes of said first periphery logic transistors comprise N+ silicon germanium; and a majority of said gate electrodes of said second periphery logic transistors comprise P+ silicon germanium.
 24. The memory device of claim 17, wherein said gate electrode of at least one of said memory array access transistor, said first periphery logic transistor, and said second periphery logic transistor, comprises a conductive layer over layer of said midgap material.
 25. A DRAM device, comprising: an access transistor having a gate electrode comprising a midgap material containing at least two material components, said gate electrode of said access transistor having a tailored workfunction, said workfunction being tailored in accordance with the mole fraction of said midgap material components of said gate electrode.
 26. The DRAM device of claim 25, wherein the threshold voltage of said access transistor is set at least in part by said mole fraction of said midgap material components of said gate electrode and an accordingly reduced amount of channel dopant.
 27. The DRAM device of claim 26, wherein said access transistor has improved refresh characteristics.
 28. The DRAM device of claim 26, wherein said access transistor is on the same integrated circuit as a periphery NMOS transistor and a periphery PMOS transistor, said periphery NMOS transistor and said periphery PMOS transistor each comprising a gate electrode, wherein each said gate electrode comprises a midgap material containing at least two material components.
 29. The DRAM device of claim 28, wherein said midgap material comprises silicon germanium.
 30. The DRAM device of claim 28, wherein said mole fraction of said midgap material components of said gate electrode of said access transistor is such that said threshold voltage of said access transistor is about 200-800 mV higher than the threshold voltage of said periphery NMOS transistor.
 31. The DRAM device of claim 29, wherein said mole fraction of said silicon germanium of said access transistor is within the range of 0.0 to 0.7 germanium.
 32. The memory device of claim 31, wherein said mole fraction of said silicon germanium of said access transistor is at least 0.2 germanium.
 33. The memory device of claim 32, wherein said silicon germanium of said memory array access transistor comprises about 30% germanium and 70% silicon.
 34. The DRAM device of claim 31, wherein said gate electrode of said access transistor comprises P+ silicon germanium; said gate electrode of said periphery NMOS transistor comprises P+ silicon germanium; and said gate electrode of said periphery PMOS transistor comprises P+ silicon germanium.
 35. The DRAM device of claim 31, further comprising a plurality of said periphery NMOS and periphery PMOS transistors, wherein said gate electrode of said access transistor comprises P+ silicon germanium; a majority of said gate electrodes of said periphery NMOS transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said periphery NMOS transistors comprise P+ silicon germanium; and a majority of said gate electrodes of said periphery PMOS transistors comprise P+ silicon germanium, and a minority of said gate electrodes of said periphery PMOS transistors comprise N+ silicon germanium.
 36. The DRAM device of claim 31, further comprising a plurality of periphery NMOS transistors and PMOS transistors, wherein said gate electrode of said access transistor comprises either N+ or P+ silicon germanium; a majority of said gate electrodes of said periphery NMOS transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said periphery NMOS transistors comprise P+ silicon germanium; and said gate electrodes of said periphery PMOS transistors comprise either P+ or N+ silicon germanium.
 37. The DRAM device of claim 31, further comprising a plurality of said periphery NMOS transistors and periphery PMOS transistors, wherein said gate electrode of said access transistor comprises P+ silicon germanium; said gate electrodes of said periphery NMOS transistors comprise N+ silicon germanium; and a majority of said gate electrodes of said periphery PMOS transistors comprise P+ silicon germanium.
 38. The DRAM device of claim 29, wherein said gate electrode of at least one of said access transistor, said periphery NMOS transistor, and said periphery PMOS transistor, comprises a conductive layer over said silicon germanium.
 39. A DRAM access transistor having improved refresh, comprising: a gate electrode having a tailored workfunction; said workfunction of said gate electrode being tailored in accordance with the mole fraction of a midgap material comprising said gate electrode, said midgap material containing at least two material components; the threshold voltage of said access transistor being set at least in part by said mole fraction of said midgap material components.
 40. The DRAM access transistor of claim 39, wherein said gate electrode comprises a material selected from the group consisting of P+ silicon germanium, N+ silicon germanium, P+ poly, and a combination of titanium nitride and tungsten.
 41. The DRAM access transistor of claim 40, wherein said midgap material comprises silicon germanium and said mole fraction of said silicon germanium of said access transistor is within the range of 0.0 to 0.7 germanium.
 42. The DRAM access transistor of claim 41, wherein said mole fraction of said silicon germanium of said access transistor is at least 0.2 germanium.
 43. The DRAM access transistor of claim 42, wherein said silicon germanium of said access transistor comprises about 30% germanium and 70% silicon.
 44. The DRAM access transistor of claim 39, wherein said gate electrode comprises a conductive layer over said midgap material.
 45. A DRAM access transistor having a gate electrode comprising P+ polysilicon.
 46. The DRAM access transistor of claim 45, wherein the threshold voltage is set by an ion implant of material selected from the group comprising antimony and arsenic.
 47. The DRAM access transistor of claim 46, further comprising source and drain regions having very shallow LDD implants and a boron deep punchthrough implant.
 48. The DRAM access transistor of claim 47, wherein said access transistor is on the same integrated circuit as a periphery NMOS transistor and a periphery PMOS transistor.
 49. A processor system, comprising: a processor; and a memory circuit coupled to said processor, at least one of said memory circuit and said processor comprising: an access transistor having a gate electrode comprising a midgap material containing at least two material components, the threshold voltage of said gate electrode of said access transistor being set at least in part by the mole fraction of said midgap material components of said gate electrode of said access transistor and an accordingly reduced amount of channel dopant; a periphery NMOS transistor having a gate electrode comprising a midgap material containing at least two material components, the threshold voltage of said gate electrode of said periphery NMOS transistor being set at least in part by the mole fraction of said midgap material components of said gate electrode of said NMOS transistor and an accordingly reduced amount of channel dopant; and a periphery PMOS transistor having a gate electrode comprising a midgap material containing at least two material components, the threshold voltage of said gate electrode of said periphery PMOS transistor being set at least in part by the mole fraction of said midgap material components of said gate electrode of said PMOS transistor and an accordingly reduced amount of channel dopant.
 50. The processor system of claim 49, wherein said midgap material comprises silicon germanium.
 51. The processor system of claim 49, wherein said mole fraction of said midgap material components of said gate electrode of said access transistor is such that said threshold voltage of said access transistor is about 200-800 mV higher than said threshold voltage of said periphery NMOS transistor.
 52. The processor system of claim 50, wherein said mole fraction of said silicon germanium of said access transistor is within the range of 0.0 to 0.7 germanium.
 53. The processor system of claim 52, wherein said mole fraction of said silicon germanium of said access transistor is at least 0.2 germanium.
 54. The processor system of claim 53, wherein said silicon germanium of said access transistor comprises about 30% germanium and 70% silicon.
 55. The processor system of claim 50, wherein said gate electrode of said access transistor further comprises a conductive layer over said silicon germanium.
 56. The processor system of claim 52, wherein said gate electrode of said access transistor comprises P+ silicon germanium; said gate electrode of said periphery NMOS transistor comprises P+ silicon germanium; and said gate electrode of said periphery PMOS transistor comprises P+ silicon germanium.
 57. The processor system of claim 52, further comprising a plurality of periphery NMOS and PMOS transistors wherein said gate electrode of said access transistor comprises P+ silicon germanium; a majority of said gate electrodes of said periphery NMOS transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said periphery NMOS transistors comprise P+ silicon germanium; and a majority of said gate electrodes of said periphery PMOS transistors comprise P+ silicon germanium, and a minority of said gate electrodes of said periphery PMOS transistors comprise N+ silicon germanium.
 58. The processor system of claim 52, further comprising a plurality of periphery NMOS and periphery PMOS transistors wherein said gate electrode of said access transistor comprises either N+ or P+ silicon germanium; a majority of said gate electrodes of said periphery NMOS transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said periphery NMOS transistors comprise P+ silicon germanium; and said gate electrodes of said periphery PMOS transistors comprise either P+ or N+ silicon germanium.
 59. The processor system of claim 52, further comprising a plurality of periphery NMOS transistors and periphery PMOS transistors wherein said gate electrode of said access transistor comprises P+ silicon germanium; said gate electrodes of said periphery NMOS transistors comprise N+ silicon germanium; and a majority of said gate electrodes of said periphery PMOS transistors comprise P+ silicon germanium.
 60. The processor system of claim 49, wherein said processor and said memory circuit are integrated on a single chip.
 61. A method of forming an access transistor of a DRAM, comprising: forming a gate electrode of said access transistor, said gate electrode of said access transistor comprising a midgap material containing at least two material components; tailoring the workfunction of said gate electrode by controlling the mole fraction of said midgap material components; setting the threshold voltage of said access transistor at least in part by said controlling of said mole fraction of said midgap material components.
 62. The method of claim 61, wherein said midgap material comprises silicon germanium.
 63. The method of claim 62, wherein act of forming said gate electrode of said access transistor comprises depositing said silicon germanium, said depositing comprising rapid thermal chemical vapor deposition or low pressure chemical vapor deposition.
 64. The method of claim 62, wherein act of forming said gate electrode of said access transistor comprises depositing polysilicon and implanting said germanium into said polysilicon.
 65. The method of claim 62, wherein said mole fraction of said silicon germanium of said access transistor is within the range of 0.0 to 0.7 germanium.
 66. The method of claim 65, wherein said mole fraction of said silicon germanium of said access transistor is at least 0.2 germanium.
 67. The method of claim 66, wherein said silicon germanium of said access transistor comprises about 30% germanium and 70% silicon.
 68. The method of claim 65, wherein said midgap material comprises P+ silicon germanium.
 69. The method of claim 65, wherein said midgap material comprises N+ silicon germanium.
 70. The method of claim 62, wherein act of forming said gate electrode further comprises forming a conductive layer over said silicon germanium.
 71. A method of forming a semiconductor device, comprising: forming a gate electrode of an access transistor, said gate electrode of said access transistor comprising a midgap material containing at least two material components; forming a gate electrode of a periphery NMOS logic transistor, said gate electrode of said periphery NMOS logic transistor comprising a midgap material containing at least two material components; forming a gate electrode of a periphery PMOS logic transistor, said gate electrode of said periphery PMOS logic transistor comprising a midgap material containing at least two material components; tailoring the workfunction of each said gate electrode at least in part by controlling the mole fraction of said midgap material components of each said gate electrode; setting the threshold voltage of each said transistor at least in part by said controlling of said mole fraction of said midgap materials of each said gate electrode.
 72. The method of claim 71, wherein said midgap material comprises silicon germanium.
 73. The method of claim 71, wherein act of setting the threshold voltage of each said transistor results in said threshold voltage of said access transistor being about 200-800 mV higher than said threshold voltage of said periphery NMOS logic transistor.
 74. The method of claim 72, wherein act of forming said gate electrode of each said transistor comprises depositing said silicon germanium, said depositing comprising rapid thermal chemical vapor deposition or low pressure chemical vapor deposition.
 75. The method of claim 72, wherein act of forming said gate electrodes of each said transistor comprises depositing polysilicon and implanting said germanium into said polysilicon.
 76. The method of claim 72, wherein said mole fraction of said silicon germanium of said access transistor is within the range of 0.0 to 0.7 germanium.
 77. The method of claim 76, wherein said mole fraction of said silicon germanium of said access transistor is at least 0.2 germanium.
 78. The method of claim 77, wherein said silicon germanium of said access transistor comprises about 30% germanium and 70% silicon.
 79. The method of claim 76, wherein said gate electrode of said access transistor comprises P+ silicon germanium; said gate electrode of said periphery NMOS logic transistor comprises P+ silicon germanium; and said gate electrode of said periphery PMOS logic transistor comprises P+ silicon germanium.
 80. The method of claim 76, further comprising forming a plurality of said periphery NMOS logic transistors and periphery PMOS logic transistors wherein said gate electrode of said access transistor comprises P+ silicon germanium; a majority of said gate electrodes of said periphery NMOS logic transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said periphery NMOS logic transistors comprise P+ silicon germanium; and a majority of said gate electrodes of said periphery PMOS logic transistors comprise P+ silicon germanium, and a minority of said gate electrodes of said periphery PMOS logic transistors comprise N+ silicon germanium.
 81. The method of claim 76, further comprising forming a plurality of said periphery NMOS logic transistors and periphery PMOS logic transistors wherein said gate electrode of said access transistor comprises either N+ or P+ silicon germanium; a majority of said gate electrodes of said periphery NMOS logic transistors comprise N+ silicon germanium, and a minority of said gate electrodes of said periphery NMOS logic transistors comprise P+ silicon germanium; and said gate electrodes of said periphery PMOS logic transistors comprise either P+ or N+ silicon germanium.
 82. The method of claim 76, further comprising forming a plurality of said periphery NMOS logic transistors and periphery PMOS logic transistors wherein said gate electrode of said access transistor comprises P+ silicon germanium; said gate electrodes of said periphery NMOS logic transistors comprise N+ silicon germanium; and a majority of said gate electrodes of said periphery PMOS logic transistors comprise P+ silicon germanium.
 83. The method of claim 72, wherein act of forming said electrode of each said transistor further comprises forming a conductive layer over layer of said silicon germanium.
 84. A method of forming a DRAM access transistor, comprising: providing a semiconductor substrate; providing a gate oxide over said semiconductor substrate; forming a P+ silicon germanium layer over said gate oxide to form a gate electrode of said access transistor; controlling the mole fraction of said germanium deposited to form said gate electrode to tailor the workfunction of said gate electrode; and setting the threshold voltage of said access transistor in accordance with said tailored workfunction of said gate electrode and by reducing the concentration of implanted enhancement dopant for the channel of said transistor in accordance with the mole fraction of said germanium.
 85. The method of claim 84, wherein act of forming said gate electrode further comprises forming a conductive layer over said silicon germanium layer and forming an oxide cap over said conductive layer.
 86. The method of claim 85, wherein said conductive layer is polysilicon.
 87. The method of claim 84, wherein act of forming said gate electrode comprises depositing said silicon germanium by rapid thermal chemical vapor deposition or low pressure chemical vapor deposition.
 88. The method of claim 84, wherein act of forming said gate electrode comprises depositing said silicon germanium by depositing polysilicon and implanting said germanium into said polysilicon.
 89. The method of claim 84, wherein said mole fraction of said silicon germanium of said access transistor is within the range of 0.0 to 0.7 germanium.
 90. The method of claim 89, wherein said mole fraction of said silicon germanium of said access transistor is at least 0.2 germanium.
 91. The method of claim 90, wherein said silicon germanium of said access transistor comprises about 30% germanium and 70% silicon.
 92. A method of improving DRAM access transistor refresh, comprising: reducing the concentration of dopant for the channel region of said access transistor; depositing a midgap material containing at least two material components to form a gate electrode of said access transistor; and tailoring the workfunction of said gate electrode by controlling the mole fraction of said midgap material components, wherein the threshold voltage of said gate electrode is set at least in part by said mole fraction of said midgap material components and said concentration of said dopant is reduced in accordance with said mole fraction of said midgap material components.
 93. The method of claim 92, wherein said midgap material is P+ silicon germanium.
 94. The method of claim 93, wherein act of depositing said silicon germanium comprises rapid thermal chemical vapor deposition or low pressure chemical vapor deposition.
 95. The method of claim 93, wherein act of depositing said silicon germanium comprises depositing polysilicon and implanting said germanium into said polysilicon.
 96. The method of claim 93, wherein said mole fraction of said silicon germanium of said access transistor is within the range of 0.0 to 0.7 germanium.
 97. The method of claim 96, wherein said mole fraction of said silicon germanium of said access transistor is at least 0.2 germanium.
 98. The method of claim 97, wherein said silicon germanium of said access transistor comprises about 30% germanium and 70% silicon.
 99. The method of claim 93, wherein act of forming said gate electrode further comprises forming a conductive layer over said silicon germanium layer. 